Elevated source drain disposable spacer CMOS

ABSTRACT

In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and drain extension regions. Thereafter source and drain contact regions are formed at a temperature up to about 600° C. and an annealing time of up to about one minute.

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This application is related to U.S. patent application Ser. No.09/736,877, titled: SACRIFICIAL POLYSILICON SIDEWALL PROCESS AND RAPIDTHERMAL SPIKE ANNEALING FOR ADVANCE CMOS FABRICATION, filed Dec. 14,2000, hereby incorporated by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] Not Applicable

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The present invention relates to a method of making CMOS devices,and more particularly, to one with an elevated source and drain andoptionally having a halo region.

[0005] 2. Description of the Related Art Including Information DisclosedUnder 37 CFR 1.97 and 1.98

[0006] As CMOS technology becomes smaller, e.g., less than 50 nm gatelength, it becomes more and more difficult to improve the short channeldevice performance and at the same time maintain acceptable values foroff-state leakage current.

[0007] One technique for trying to achieve this is the halo techniquewherein extra dopant implant regions are next to the sources and drainextension regions. For this to work the junctions must be abrupt, see“CMOS Devices below 0.1 nm: How High Will Performance Go?”, by Y. Taur,et al., pp. 1-4. In particular, for sub 50 nm devices, not only theextension regions near the channel must be abrupt, i.e., less than 4nm/decade, but the halo profile in proximity to the extension junctionmust be abrupt, i.e., less than 20 nm/decade.

[0008] Most of the prior art for the halo formation used a generalapproach wherein halo dopants are implanted at an angle ranging from 0°to 70° into the channel region. This prior art varied either the dose,halo dopants, or angle of halo implants for improving the deviceperformance. The article “Halo Doping Effects in Submicron DI-LDD DeviceDesign” by Christopher Codella et al., pp. 230-233, describes theoptimum halo doses for improving the threshold voltage and thepunch-through device characteristics. Punch-through stoppers was alsodiscussed in the U.S. Pat. No. 5,320,974 by Atsushi Hori et al. which issimilar to the conventional halo arrangements. The article “A 0.1 nmIHLATI (Indium Halo by Large Angle Tilt Implant) MOSFET for 1.0V LowPower Application” by Young Jin Choi et al. described the use of anindium halo and a large angle tilt for indium halo implants forimproving the short channel characteristics. Other articles are “HighCarrier velocity and Reliability of Quarter-Micron SPI (Self-AlignedPocket Implantation) MOSEFETs” by A. Hori et al. and “A 0.1-μm CMOSTechnology with Tilt-Implanted Punchthrough Stopper (TIPS)” by T. Hori.

[0009] None of the prior art focussed attention on improving theabruptness of the halo dopant profiles in the area next to the channel.In these prior art situations, the halo dopants would have sufferedenhanced transient diffusion and/or deactivation during contact andextension junction formation, and high thermal budget deep source/dranrapid thermal anneal (RTA) (typically 1000° C. for 5 seconds).Consequently, these much degraded halos severely compromised theirusefulness for improving the short channel device characteristics, andthis is especially the case for device channel width below 50 nm. Thusall the prior art approaches provide no means to minimize transientenhanced diffusion and/or deactivation of the halo dopants and hencecannot be used to create the abrupt super-halo (<20 nm/decade) in theregion next to the channel area.

[0010] It is therefore desirable to have a process for making abruptshallow PN junctions and haloes which does not cause dopant diffusion ordeactivation.

BRIEF SUMMARY OF THE INVENTION

[0011] A method comprises forming source and drain regions; andthereafter forming source and drain extension regions.

[0012] A method comprises forming elevated and deep source and drainregions; forming source and drain extension regions; and thereafterforming source and drain contact regions at a temperature up to about600° C. and an annealing time up to about one minute.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0013]FIGS. 1-6 show a process in accordance with first embodiment ofthe invention;

[0014] FIGS. 7(a) and 7(b) are graphs of etch rates;

[0015] FIGS. 8(a) and 8(b) are graphs of resistance verses RTA times;

[0016]FIGS. 9-13 show a second embodiment of the invention;

[0017]FIGS. 14-16 show a third embodiment of the invention;

[0018]FIGS. 17 and 18 show a fourth embodiment of the invention;

[0019]FIGS. 19-21 show a fifth embodiment of the invention;

[0020]FIGS. 22-24 show a sixth embodiment;

[0021]FIGS. 25-27 show a seventh embodiment;

[0022]FIGS. 28-31 show an eighth embodiment;

[0023] FIGS. 32 shows a ninth embodiment;

[0024]FIGS. 33-36 show a tenth embodiment; and

[0025]FIGS. 37-39 show an eleventh embodiment.

DETAILED DESCRIPTION OF THE INVENTION

[0026] As shown in FIG. 1, silicon oxide with a thickness of betweenabout 500 to 1000 nm as an insulating film for separating elements isformed in an element separation shallow trench isolation (STI) regions10 a and 10 b of a P-type single crystal silicon semiconductor substrate12. Silicon oxide film with a thickness of between about 1 to 3 nm as agate insulating film is formed on an active region of the substrate 10.Then it is etched using known techniques to form the gate insulatinglayer 14. Then a gate electrode 16 with a thickness of between about 100to 150 nm is formed by etching a deposited polycrystalline silicon filmin ordinary photolithography and etching processes. A reoxidation isthen done to form layer 18. Upon gate 16 is deposited the thin insulatorfirst layer 20, preferably silicon nitride, which can be produced bychemical vapor deposition, sputtering, or related techniques. The layer20 has a thickness of between about 5 nm to 50 nm, preferably betweenabout 10-30 nm. Upon the layer 20 is deposited a second layer ofmaterial, such as SiO_(x), a-Si, or polysilicon. In particular, thislayer has a thickness of about between about 50 to 150 nm. This secondlayer is then defined by reactive ion etching (RIE) using a highlyselective etch, e.g., p-Si etches at a rate about 200 times faster thanSi₃N₄, thereby resulting in sidewalls 22 a and 22 b (FIG. 2) withoutdamaging layer 20. During these etching steps, layer 20 acts as an etchstop layer.

[0027] After spacer formation, ion implantation is performed tointroduce dopants into substrate 12 forming regions 24 a and 24 b, (FIG.3), which are spaced away from the edge of the gate 16 by a distancedefined by the width of spacers 22 and layer 20. In one particularmethod, arsenic (As) ions are implanted into the substrate 12 at a doseof between about 3 to 10×10¹⁵/cm² at about 50 KeV using the gateelectrode 16 and the side wall spacers 22 as a mask, thereby forming anN⁺-type deep source 24 a and drain deep 24 b regions. During this step,gate 16 is also ion implanted to make it a good conductor. For P⁺source/drain formation, B ions may be implanted at about 10 KeV with adose of about 3 to 10×10¹⁵/cm².

[0028] After formation of doped source/drain contact regions 24, thesidewall spacers 22 are selectively removed by well known methods suchas reactive ion etching, or wet methods, the later preferably using asolution of KOH in the case of a polysilicon spacer, or HF in the caseof an oxide spacer. The resulting structure, as shown in FIG. 4,contains implanted liner layer areas 20 a as well as unimplanted linerlayer areas 20 b, which remain substantially unimplanted because ofabsorption of ions in the spacers 22 during the implantation step.

[0029] The next step comprises selective removal of the implanted linerareas 20 a, leaving the unimplanted liner 20 b intact. This ispreferably accomplished by using hot phosphoric acid (H₃PO₄) at about160° C. for between about 1 to 5 minutes, in the case where the liner 20is silicon nitride. As FIG. 7(a) shows, the etch rate 702 of theimplanted and unannealed nitride is much greater than the etch rate 704for unimplanted nitride for both N-type and P-type dopants, while theetch rate 706 for implanted and annealled nitride is about the same asthe etch rate 704 for unimplanted nitride. FIG. 7(b) shows that thenitride etch rate 708 for rapid thermal chemical vapor deposition(RTCVD) is about the same as the etch rate 710 for plasma enhancedchemical vapor deposition (PECVD). Thus, either RTCVD or PECVD can beused as a suitable layer in which the implantation causes a largeincrease in etch rate. Hence, removal of 200 Å layer 20 a of N⁺ or P⁺implanted nitride at 160° C., would only remove about 35 Å or so Å,respectively, of the unimplanted layer 20 b. A similar procedure couldbe performed using HF to selectively remove an implanted oxide layerwith respect to an unimplanted oxide liner.

[0030] After selective removal of areas 20 a, then the structure may beannealed between about 1000° C. and 1100° C., preferably about 1000° C.,for between about 1 to 10 seconds, preferably about 5 seconds, toactivate the source/drain 24 and gate 16 regions.

[0031] Any residual thin layer, such as less than 50 Å of oxide layers14 and 18 is removed from on top of regions 16 and 24 by etching in HF.Subsequently, as shown in FIG. 5, silicide contacts 32 a, 32 b, and 32 care formed on the gate 16 (in the case of polysilicon gate) and sourceand drain regions 24 by well known self-aligned processes, such assalicide or direct selective CVD. Both processes are selective such thatno silicide or metal remains on liner 20 b, which is subsequentlyremoved by wet etching using phosphoric acid in the case of nitride.Final steps involve ion implantation of shallow source/drain extensionregions 26 a and 26 b (FIG. 6), with or without halo regions 28 a and 28b, followed by high temperature annealing to activate the extension 26and halo regions 28, if present.

[0032] In particular, arsenic (As) ions are implanted at a dose of 1 to4×10¹⁵ cm⁻² at an energy of between about 2 to 10 KeV using the gateelectrode 16 as a mask thereby forming an N⁺-type source extensionregion 26 a and an N⁺-type drain extension region 26 b. Thereafter anoptional annealing step of between about 1000° C. and 1050° C.,preferably about 1000° C., for about 0 to 5 seconds, preferably about 1second, is done in order to activate extension regions 26.

[0033] Optionally, boron (B) is then implanted at an energy of betweenabout 3 to 10 KeV at a tilt angle between about 10 to 30 degrees withrespect to a normal line of a main surface of substrate 12 and with fourrotation around the normal axis and with a total a real dosage ofbetween about 5×10¹³/cm² to 5×10¹⁴/cm² to form optional halo regions 28a and 28 b. The condition of the ion implantation for forming the P⁺type halo regions 28 may be adjusted depending upon various factors suchas an impurity concentration of the substrate 12, a desired value of theinversion threshold voltage, a minimum gate length and a drainstructure. A dosage and a tilt angle of the ion implantation can beselected from a wide range. Boron fluoride ions (BF₂ ⁺) and indium (In⁺)ions are appropriate besides boron ions. Further the shape of haloregions 28 can be other than that shown as known in the art. For P⁺extension regions, BF₂ ⁺ ions may be implanted at 1 to 10 KeV at ananneal dosage of between about 5×10¹⁴/cm² to 3×10¹⁵/cm². Thereafter, Asis optionally implanted to an energy of about 3 to 30 KeV at a tiltangle of between about 10° to 30° to form N⁺-type halo regions.

[0034] Thereafter an optional spike annealing, e.g., a ramp up rate ofgreater than about 100° C./s, a hold time of about zero seconds at atarget temperature between about 800° to 1050° C., and a ramp down rategreater than about 50° C./s, is performed thus activating the dopants inthe haloes 28 and, if said optional annealing steps were not done, alsoactivate regions 24, 26, and gate 16. However, other types of annealingcan be used. Further, separate annealing steps can be used forextensions 26 and haloes 28.

[0035] Spike annealing can be done by high powered tungsten (w) lamps,arc lamps, or excimer laser operating in the non-melting mode, e.g. lessthan 750 mJ/cm². Spike annealing has two advantages. One is that thewafer can get up to the high target temperature quickly so that thedefect annealing with a higher activation energy (−5 ev) can be carriedout with less time spent for undesirable halo dopant annealing with lessactivation energy (<4 eV). The second advantage of the spike anneal isthe obvious advantage of much reduced thermal cycle due to the rapidthermal anneal cycle. As a result, the halo dopant motion during rapidthermal annealing is much reduced.

[0036] Conventional silicide of thickness less than 40 nm (11 nm Cothickness since the silicide thickness is 3.6 times the Co thickness) asshown in FIG. 8(a) is not stable, i.e., its resistivity increases withRTA hold time. Hence, if conventional silicide is used, it must bethicker than 40 nm to be stable during the extension anneal, whichoccurs subsequent to silicide formation. In order to form such a thicksilicide, thick source and drain regions 24 and 26 must be used sincethey are partially consumed in silicide formation, or otherwise theywill have an undesirably high resistance. But, if regions 24 and 26 arethick, then larger sidewall spacers 22 are needed, thereby resulting inan undesirably larger device. The current embodiment uses a hightemperature-stable conductor, e.g. a silicide, which may comprise aternary Si alloy, which is stable during high temperature annealing,such that the silicide layer 32 remains intact and still highlyconductive after the final annealing steps are performed. As shown inFIG. 8(b), a known 5% Re alloy in Co as disclosed in U.S. patentapplication Ser. No. 09/519,898, filed Mar. 6, 2000, hereby incorporatedby reference, is effective in accomplishing this. A key device advantageof the process and structure described in FIGS. 1 to 6 is that thesilicide processing takes place before regions 24, 26, and, if present,28 are formed, so that no high temperature steps which could degraderegions 24, 26 and 28 take place subsequent to formation of the latter.

[0037] In a second embodiment of the invention, the process is the sameas in the first embodiment up to FIG. 4. Thereafter, regions 20 a areselectively removed as shown in FIG. 9 Regions 33 a, 33 b, and 33 ccomprising a selective silicon (or SiGe), preferably having a thicknessof between about 50-1000 Å, are then formed on the source and drainregions 24 and on the gate 16, instead of silicide as describe in thefirst embodiment (FIG. 10). This is accomplished by well known CVDtechniques at temperatures ranging from between about 550° C.-1000° C.preferably between about 700 and 900° C. An advantage of the currentinvention is that formation of regions 33, which often takes place attemperatures in excess of 900° C., occurs before formation of regions24, 26, and 28 so that these regions 24, 26 and 28 are not degraded byhigh temperature processing after initial formation. Subsequent toselective silicon deposition to form an elevated source and drainstructure, a shallow implant is done in regions 33 (FIG. 11). Thensilicide formation takes place as in the first embodiment (FIG. 12),i.e., forming silicide within regions 33 and possibly extending intoregion 24. Then follows formation of regions 26 a and 26 b after removalof spacer 20 b (FIG. 13). The advantage of the process of the secondembodiment is that an elevated source/drain device is formed with allhigh temperature processes (generally defined as between about 600-1000°C. for silicide and selective silicon) taking place before regions 26formation, ensuring maximum abruptness and activation of these regions.Another advantage of the present structure is that it provides a sourcefor extra-thick silicide (in this embodiment the preferred silicidethickness is between about 40-60 nm) without penetration far into theregions 24, thus providing a more stable silicide layer for subsequenthigh temperature annealing.

[0038] In a third embodiment, the process starts as in the secondembodiment up to FIG. 10. The next step is removal of layer 20 b (FIG.14). Thereafter regions 26 and simultaneously contacts 33 are implanted(FIG. 15). Annealing to activate the dopants is done, and then permanentspacers 22 a and 22 b are formed using a typical material such as oxideor nitride, and subsequent silicide formation by known methods (FIG.16). The advantage of this embodiment is that it does not require thesilicide to withstand high temperature SDE/halo dopant activationanneals, but a preferred silicide material for this embodiment is NiSi,which forms at between about 400° C. to 600° C., for between 10 to 60seconds, and does not deleteriously affect the SDE/Halo even though itoccurs after halo formation.

[0039] A fourth embodiment follows the sequence of the second embodimentup to all of the steps of FIG. 12. The next step is selective removal ofthe horizontal portion of layer 20 b, which is accomplished preferablyby reactive ion etching, leaving the vertical portion of the layer 20 inplace as sidewalls 20 c (FIG. 17). Subsequent ion implantation ofregions 24 and 26 is performed and junctions are activated (FIG. 18).The advantage of this process is that it allows the dopants to beimplanted at some distance laterally away from the gate edge, defined bythe width of the nitride spacer 20 c. This would be useful forfast-diffusing dopants such as B, where formation might result in toomuch overlap of regions 24 and 26 under the gate 16 after annealing,resulting in higher overlap capacitance.

[0040] In a fifth embodiment the previous steps are followed up to FIG.10. Then the horizontal portion of nitride layer 20 b is removed (FIG.19) resulting in sidewalls 20 c, followed by SDE/halo formation ofregion 26 (FIG. 20), permanent spacer 22 having portions 22 a and 22 b,(FIG. 21) and low temperature silicide contacts 32. This process differsfrom the fourth embodiment only in the use of a low temperature silicideat the end, and removes the need of ensuring high temperature silicidestability, and is preferably accomplished using low temperature silicidesuch as NiSi or PtSi.

[0041] In a sixth embodiment, the previous steps are followed up to FIG.20, after which a second selective layer 34, having sections 34 a, 34 b,and 34 c, preferably Si or SiGe, of preferably between about 10-50 μmthickness, is grown, resulting in a stepped elevated source drainstructure. The growth is preferably done using low temperature Si orSiGe, which can be done at between about 500-650° C., causing minimalimpact on the regions 24 and 26 (FIG. 22). The second silicon layer 34can subsequently be implanted (FIG. 23), followed by activationannealing forming regions 26 in the elevated region near the gate 16,and ending with the formation of permanent spacer 22 with portions 22 aand 22 b (FIG. 24) and low temperature silicide. This technique producesa structure which has low SDE resistance because of the elevation nearthe gate 16, but decouples the amount of silicon used to form thesilicide contacts 32 with the amount of silicon near the gate 16, andthereby allows the overlap capacitance to be less than in a non-steppedstructure.

[0042] A seventh embodiment of the current invention involves followingthe preceding steps up to FIG. 19, but then depositing (FIG. 25), thesecond selective Si layer 34 having sections 34 a, 34 b, and 34 c beforeimplantation of regions 24 and 26, using etch to remove remainingnitride layer 20 (FIG. 26) next to the gate 16, and SDE formation, suchthat SDE ions can be located adjacent to the gate 16 edge with very lowenergy implant. This is followed by permanent sidewall spacer 22 havingportions 22 a and 22 b formation (FIG. 27) and low temperature silicidecontacts 32 formation, preferably using NiSi, PtSi, or relatedmaterials.

[0043] An eighth embodiment involves following the preceding steps up toFIG. 17, followed by selective deposition of silicon layer 35 (FIG. 28),which in addition to growing in the exposed Si area immediately adjacentto the gate 16, also may grow on the already present silicide in thesource and drain 26 and 24 and gate 16 areas, since selective Siprocesses are selective to nitride and oxide, but may typically grow onsilicide. The subsequent structure may be then implanted and annealed(FIG. 29). Then the thin nitride layer 20 removed (FIG. 30), followed byimplantation of regions 27 for formation closer to the gate 16 (FIG.31). The silicide layer 32 is buried before SDE anneal and will be morethermally stable, while the structure resulting is ideal from anelectrical design, with low SDE resistance, low overlap capacitance, andability to form ultra shallow junctions immediately adjacent to the gate16 with no subsequent high temperature processing. The buried silicidelayer 32 can easily be contacted by usual lithography and etch stepswhich will selectively remove the silicon layer 35 and leave thesilicide layer 32 intact.

[0044] A ninth embodiment involves the previous steps up to FIG. 29,followed by ion implantation to form regions 28. In this embodiment, thevertical spacer 20 c is retained in order to keep fast moving dopantsfrom diffusing too far under gate 16 (FIG. 32).

[0045] In the tenth embodiment, the steps are the same up to FIG. 4followed by RIE to remove the horizontal portion of spacer 20 b (FIG.33). This is followed by selective Si growth (FIG. 34), implantationinto region 33 and annealing (FIG. 35). Then permanent spacer 22formation and low temperature silicide formation (FIG. 36) is done.

[0046] In the eleventh embodiment the steps are the same up to FIG. 35.Layer 20 b is then selectively removed (FIG. 37), followed byimplantation and annealing, which forms regions 27 near the edge of gate16 (FIG. 38). This is followed by permanent spacer 22 and silicideformation (FIG. 39).

[0047] It will be appreciated that substrate 12 can also be of othergroup IV materials, e.g., C, Ge, SiGe alloy, Si-on-insulator (SOI),etc,; a group III-V material, e.g. GaAs, InP, AlGaAs, etc.; or a groupII-VI material. Also for the P-type dopant B, In, Al and Ga can be used,while for the N-type dopant P, As, Sb can be used. Further, althoughmost of the description is directed to N-channel devices, the presentinvention can be used to make P-channel devices by reversingconductivity types.

[0048] For the conductors, including gate 16, W, Al, Cu, Ti, Nii P-SiGealloy, heavily doped p-Si or a-Si, and combinations thereof can be used.

[0049] Further, the present invention can also be used in any devicewith a PN junction, e.g., diodes, bipolar transistors, etc.

[0050] While the present invention has been particularly described withrespect to preferred embodiments, it will be understood that theinvention is not limited to these particular preferred embodiments, theprocess steps, the sequence, or the final structures depicted in thedrawings. On the contrary, it is intended to cover all alternatives,modifications, and equivalents as may be included within the spirit andscope of the invention defined by the appended claims. In addition,other methods and/or devices may be employed in the method and apparatusof the instant invention as claimed with similar results.

What is claimed is:
 1. A method for patterning a hard mask comprisingthe steps of: forming a first hard mask over a substrate containingfeatures, applying a second mask over said first hard mask, patterningsaid second mask, ion implanting through said first hard mask inopenings in said second mask, and selectively wet etching said firsthard mask where exposed.
 2. The method of claim 1, wherein prior to saidstep of selectively wet etching, further comprising the step of removingsaid second mask.
 3. The method of claim 1, wherein said step ofselectively wet etching includes using an etchant containing phosphoricacid.
 4. A method for forming spaced apart source and drain regionshaving areas for contact, said method comprising the steps of: selectinga silicon containing substrate, forming a dielectric layer having athickness of from about 1 to about 10 nm suitable for the gate insulatorof a field effect transistor, forming a gate electrode layer over saiddielectric layer, patterning said gate electrode layer to form a gateelectrode over said dielectric layer, forming a temporary spacer on thesidewalls of said gate electrode by forming a dielectric liner of afirst material and one of a dielectric or silicon containing layer of asecond material, anisotropic etching said second material, whereby saidsecond material forms a sidewall spacer of controlled width which isdetermined by the original thickness of the layer of said secondmaterial, performing blanket ion implantation on the resultingstructure, whereby ions pass through said dielectric liner of said firstmaterial and are substantially absorbed where incident on said sidewallspacer of said second material and whereby said liner of said firstmaterial underneath said sidewall spacer is protected, selectivelyremoving said second material with respect to said first material,selectively wet etching said first material where damaged by ionimplantation, whereby said first material remains on the sidewalls ofsaid gate electrode and remains where said first material was formerlyunderneath said second material of said sidewall spacer and protectedfrom ion implantation, and annealing said ion implanted regions in saidsilicon containing substrate to form source and drain regionselectrically contactable through openings in said first material.
 5. Themethod of claim 4, further including the step of selectively growing asilicide on said source and drain regions through openings in said firstmaterial.
 6. A method for contacting source and drain regions exposedthrough openings in a liner comprising a first material on a substratestructure, said method comprising the steps of: selectively growing asilicide on said source and drain regions through said openings in saidfirst material, and selectively removing said liner of said firstmaterial,
 7. The method of claim 6, wherein said step of implantingdopants further includes implanting dopants of a second conductivitytype to form a halo region at the gate edge of said source and drainregions.
 8. A method for contacting source and drain regions exposedthrough openings in a liner comprising a first material on a substratestructure, said method comprising the steps of: forming a blanket layerof metal over said openings, reacting said metal with said exposedsource and drain regions to form a stable silicide, selectively wetetching with respect to said stable silicide to remove unreacted metalin regions where said liner of said first material remains, selectivelyremoving said liner of said first material, implanting dopants of afirst conductivity type on either side of said gate electrode, annealingto form source drain extension regions, said step of annealing and saidmetal for said suicides selected to preserve said silicide layer fromagglomeration during said step of annealing.
 9. The method of claim 8,wherein said step of implanting dopants further includes implantingdopants of a second conductivity type to form a halo region at the gateedge of said source and drain regions.
 10. The method of claim 4,further including the steps of: selectively depositing on source anddrain openings a silicon containing semiconductor material, selectivelyremoving said liner of said first material, implanting dopants of afirst conductivity type on either side of said gate electrode, andannealing to form source and drain extension regions.
 11. The method ofclaim 10, wherein said step of implanting dopants further includesimplanting dopants of a second conductivity type to form a halo regionat the gate edge of said source and drain regions.
 12. The method ofclaim 10, wherein after the step of annealing, further comprising thesteps of: forming a gate electrode sidewall spacer, and selectivelygrowing a silicide on exposed source and drain regions adjacent saidsidewall spacers.
 13. The method of claim 10, wherein after the step ofannealing, further comprising the steps of: forming a gate electrodesidewall spacer, forming a blanket layer of metal over said openings,reacting said metal with said source and drain regions to forming astable silicide, and selectively wet etching to remove unreacted metalin regions where said spacer remains.
 14. The method of claim 10,wherein after said step of selectively depositing semiconductormaterial, further comprising the steps of: forming a gate electrodesidewall spacer, forming a blanket layer of metal over said openings,reacting said metal with said source and drain regions to forming astable silicide, and selectively wet etching to remove unreacted metalin regions where said spacer remains.
 15. The method of claim 10,wherein after step of selectively depositing silicon containingsemiconductor material on source and drain openings, further comprisingthe-step of implanting dopants of a first conductivity type into saidselectively deposited silicon containing semiconductor material.
 16. Themethod of claim 15, wherein after said step of implanting dopants intosaid selectively deposited silicon, further comprising the step ofselectively removing said first liner material
 17. The method of claim15, wherein after said step of implanting dopants into said selectivelydeposited silicon,, further comprising the steps of annealing saiddopants and selectively removing said first liner material.
 18. Themethod of claim 16, wherein said step of selectively removing said firstliner material further comprises the steps of implanting dopants of saidfirst conductivity type on either side of said gate electrode, andannealing said implanted dopants to form source and drain extensions.19. The method of claim 18, wherein after implanting ions of firstconductivity type, further comprising the steps of implanting ions of asecond conductivity type, and annealing to concurrently form a haloregion and drain and source extensions at the gate edge.
 20. The methodof claim 17, wherein said step of selectively removing said first linermaterial further comprises the steps of implanting dopants of said firstconductivity type on either side of said gate electrode, and annealingsaid implanted dopants to form source and drain extensions.
 21. Themethod of claim 20, wherein after implanting ions of first conductivitytype, further comprising the steps of implanting ions of a secondconductivity type, and annealing to concurrently form a halo region anddrain and source extensions at the gate edge.
 22. The method of claim18, further comprising the steps of: forming a gate electrode sidewallspacer, forming a blanket layer of metal over said openings, reactingsaid metal with said source and drain regions to forming a stablesilicide, and selectively wet etching to remove unreacted metal inregions where said spacer remains.
 23. The method of claim 19, furthercomprising the steps of: forming a gate electrode sidewall spacer,forming a blanket layer of metal over said openings, reacting said metalwith said source and drain regions to form a stable silicide, andselectively wet etching to remove unreacted metal in regions where saidspacer remains.
 24. The method of claim 20, further comprising the stepsof: forming a gate electrode sidewall spacer, forming a blanket layer ofmetal over said openings, reacting said metal with said source and drainregions to forming a stable silicide, and selectively wet etching toremove unreacted metal in regions where said spacer remains.
 25. Themethod of claim 21, further comprising the steps of: forming a gateelectrode sidewall spacer, forming a blanket layer of metal over saidopenings, reacting said metal with said source and drain regions to forma stable silicide, and selectively wet etching to remove unreacted metalin regions where said spacer remains.
 26. The method of claim 10,wherein after said step of selectively depositing said silicon material,further comprising the steps of: forming a blanket layer of metal oversaid openings, reacting said metal with said source and drain regions toform a stable silicide, selectively wet etching to remove unreactedmetal in regions where said liner of first material remains, andselective removal of said first liner.
 27. The method of claim 26,wherein after the selective removal of said first liner, furthercomprising the steps of ion implanting dopants of said firstconductivity type on either side of said gate electrode, and annealingsaid implanted dopants to form source and drain extensions.
 28. Themethod of claim 27, wherein after implanting ions of first conductivitytype, further comprising the steps of: implanting ions of a secondconductivity type, and annealing to concurrently form a halo region anddrain and source extensions at the gate edge.
 29. The method of claim15, wherein after said step of ion implantation, further comprising thesteps of: forming a blanket layer of metal over said openings, reactingsaid metal with said source and drain regions to form a stable silicide,selectively wet etching to remove unreacted metal in regions where saidliner of first material remains, and selectively removing said firstliner such that implanted silicon region in said liner openings isprotected by said stable silicide during liner removal process.
 30. Themethod of claim 17, wherein after said step of annealing of dopants,further comprising the steps of: forming a blanket layer of metal oversaid openings, reacting said metal with said source and drain regions toform a stable silicide, selectively wet etching to remove unreactedmetal in regions where said liner of first material remains, andselectively removing said first liner such that implanted silicon regionin said liner openings is protected by said stable silicide during linerremoval process.
 31. The method of claim 29, wherein after selectivelyremoving said first liner, further comprising the steps of ionimplanting dopants of said first conductivity type on either side ofsaid gate electrode, and annealing said implanted dopants to form sourceand drain extensions.
 32. The method of claim 30, wherein afterselectively removing said first liner, further comprising the steps ofion implanting dopants of said first conductivity type on either side ofsaid gate electrode, and annealing said implanted dopants to form sourceand drain extensions.
 33. The method of claim 31, wherein afterimplanting ions of first conductivity type, further comprising the stepsof implanting ions of a second conductivity type, and annealing toconcurrently form a halo region and drain and source extensions at thegate edge.
 34. The method of claim 32, wherein after implanting ions offirst conductivity type, further comprising the steps of implanting ionsof a second conductivity type, and annealing to concurrently form a haloregion and drain and source extensions at the gate edge.
 35. The methodof claim 10, wherein after said step of selectively depositing saidsilicon material, further comprising the steps of selectively depositinga silicide material over said openings on said selective silicon, andselective removal of liner of said first material.
 36. The method ofclaim 35, wherein after the step of selectively removing said firstliner, further comprising the steps of ion implanting dopants of saidfirst conductivity type on either side of said gate electrode, andannealing said implanted dopants to form source and drain extensions.37. The method of claim 36, wherein after implanting ions of firstconductivity type, further comprising the steps of implanting ions of asecond conductivity type, and annealing to concurrently form a haloregion and drain and source extensions at the gate edge.
 38. The methodof claim 15, wherein after said step of ion implanting in said selectivesilicon material, further comprising the steps of: selectivelydepositing a silicide material over said openings on said selectivesilicon, and selective removal of said first liner such that implantedsilicon region in said liner openings is protected by said stablesilicide during liner removal process.
 39. The method of claim 17,wherein after said step of said dopant annealing, further comprisingsteps of: selectively depositing a silicide material over said openingson said selective silicon, and selectively removing said first linersuch that implanted silicon region in said liner openings is protectedby said stable silicide during liner removal process.
 40. The method ofclaim 38, wherein after the step of selectively removing said firstliner, further comprising the steps of ion implanting dopants of saidfirst conductivity type on either side of said gate electrode, andannealing said implanted dopants to form source and drain extensions.41. The method of claim 39, wherein after the step of selective removalof said first liner further comprising the steps of ion implantingdopants of said first conductivity type on either side of said gateelectrode, and annealing said implanted dopants to form source and drainextensions.
 42. The method of claim 40, wherein after implanting ions offirst conductivity type, further comprising the steps of implanting ionsof a second conductivity type, and annealing to concurrently form a haloregion and drain and source extensions at the gate edge.
 43. The methodof claim 41, wherein after implanting ions of first conductivity type,further comprising the steps of implanting ions of a second conductivitytype, and annealing to concurrently form a halo region and drain andsource extensions at the gate edge.
 44. The method of claim 15, whereinafter said step of ion implanting in said selective silicon material,further comprising the step of selectively removing by anisotropicetching said liner of first material on horizontal surfaces such thatsaid liner of first material remains on gate electrode vertical surfacewhile remaining source and drain regions contain exposed silicon. 45.The method of claim 17, wherein after said step of dopant annealing,further comprising the step of selectively removing by anisotropicetching said liner of first material on horizontal surfaces such thatsaid liner of first material remains on gate electrode vertical surfacewhile remaining source and drain regions contain exposed silicon. 46.The method of claim 44, wherein after said anisotropic liner etching,further comprising the steps of ion implanting dopants of said firstconductivity type on either side of said gate electrode such that theimplanted ions are spaced from the gate electrode by the width of saidliner, and annealing said implanted dopants to form source and drainextensions.
 47. The method of claim 45, wherein after said anisotropicliner etching, further comprising the steps of ion implanting dopants ofsaid first conductivity type on either side of said gate electrode suchthat the implanted ions are spaced from the gate electrode by the widthof said liner, and annealing said implanted dopants to form source anddrain extensions.
 48. The method of claim 46, wherein after implantingions of first conductivity type, further comprising the steps ofimplanting ions of a second conductivity type, and annealing toconcurrently form a halo region and drain and source extensions at thegate edge.
 49. The method of claim 47, wherein after implanting ions offirst conductivity type, further comprising the steps of implanting ionsof a second conductivity type, and annealing to concurrently form a haloregion and drain and source extensions at the gate edge.
 50. The methodof claim 46, wherein after annealing said dopants, further comprisingthe following steps: forming a gate electrode sidewall spacer, forming ablanket layer of metal over said openings, reacting said metal with saidsource and drain regions to form a stable silicide, and selectively wetetching to remove unreacted metal in regions where said spacer remains.51. The method of claim 47, wherein after annealing said dopants,further comprising the following steps: forming a gate electrodesidewall spacer, forming a blanket layer of metal over said openings,reacting said metal with said source and drain regions to form a stablesilicide, and selectively wet etching to remove unreacted metal inregions where said spacer remains.
 52. The method of claim 48, whereinafter annealing said dopants, further comprising the following steps:forming a gate electrode sidewall spacer, forming a blanket layer ofmetal over said openings, reacting said metal with said source and drainregions to form a stable silicide, and selectively wet etching to removeunreacted metal in regions where said spacer remains.
 53. The method ofclaim 49, wherein after annealing said dopants, further comprising thefollowing steps: forming a gate electrode sidewall spacer, forming ablanket layer of metal over said openings, reacting said metal with saidsource and drain regions to form a stable silicide, and selectively wetetching to remove unreacted metal in regions where said spacer remains.54. The method of claim 15, wherein after said step of ion implanting insaid selective silicon material, further comprising the steps of:forming a blanket layer of metal over said openings, reacting said metalwith said source and drain regions to form a stable silicide,selectively wet etching to remove unreacted metal in regions where saidspacer remains, and selectively removing by anisotropic etching saidliner of first material on horizontal surfaces such that said liner offirst material remains on gate electrode vertical surface whileremaining source and drain regions contain exposed silicon.
 55. Themethod of claim 15, wherein after said step of ion implanting in saidselective silicon material, further comprising the steps of: selectivelydepositing silicide in said openings, and selectively removing byanisotropic etching said liner of first material on horizontal surfacessuch that said liner of first material remains on gate electrodevertical surface while remaining source and drain regions containexposed silicon.
 56. The method of claim 17, wherein after said stepdopant annealing, further comprising the steps of: forming a blanketlayer of metal over said openings, reacting said metal with said sourceand drain regions to form a stable silicide, selectively wet etching toremove unreacted metal in regions where said spacer remains, andselectively removing by anisotropic etching said liner of first materialon horizontal surfaces such that said liner of first material remains ongate electrode vertical surface while remaining source and drain regionscontain exposed silicon.
 57. The method of claim 17, wherein after saidstep dopant annealing, further comprising the steps of: selectivelydepositing silicide in said openings, and selectively removing byanisotropic etching said liner of first material on horizontal surfacessuch that said liner of first material remains on gate electrodevertical surface.
 58. The method of claim 54, wherein after saidanisotropic liner etching, further comprising the steps of: ionimplanting dopants of said first conductivity type on either side ofsaid gate electrode such that the implanted ions are spaced from thegate electrode by the width of said liner, and annealing said implanteddopants to form source and drain extensions.
 59. The method of claim 55,wherein after said anisotropic liner etching, further comprising thesteps of: ion implanting dopants of said first conductivity type oneither side of said gate electrode such that the implanted ions arespaced from the gate electrode by the width of said liner, and annealingsaid implanted dopants to form source and drain extensions.
 60. Themethod of claim 56, wherein after said anisotropic liner etching,further comprising the steps of: ion implanting dopants of said firstconductivity type on either side of said gate electrode such that theimplanted ions are spaced from the gate electrode by the width of saidliner, and annealing said implanted dopants to form source and drainextensions.
 61. The method of claim 57, wherein after said anisotropicliner etching, further comprising the steps of: ion implanting dopantsof said first conductivity type on either side of said gate electrodesuch that the implanted ions are spaced from the gate electrode by thewidth of said liner, and annealing said implanted dopants to form sourceand drain extensions.
 62. The method of claim 58, wherein afterimplanting ions of first type, further comprising the steps of:implanting ions of a second conductivity type, and annealing toconcurrently form a halo region and drain and source extensions at thegate edge.
 63. The method of claim 59, wherein after implanting ions offirst conductivity type, further comprising the steps of: implantingions of a second conductivity type, and annealing to concurrently form ahalo region and drain and source extensions at the gate edge.
 64. Themethod of claim 60, wherein after implanting ions of first conductivitytype, further comprising the steps of: implanting ions of a secondconductivity type, and annealing to concurrently form a halo region anddrain and source extensions at the gate edge.
 65. The method of claim61, wherein after implanting ions of first conductivity type, furthercomprising the steps of: implanting ions of a second conductivity type,and annealing to concurrently form a halo region and drain and sourceextensions at the gate edge.
 66. The method of claim 46, wherein aftersaid annealing, further comprising the following steps: asilicon-containing semiconductor is deposited selectively such that itdoes not grow on said selective liner on vertical gate surface,implanting ions of a first conductivity type, annealing said implants,forming a gate electrode sidewall spacer, forming a blanket layer ofmetal over said openings, reacting said metal with said source and drainregions to form a stable silicide, and selectively wet etching to removeunreacted metal in regions where said spacer remains.
 67. The method ofclaim 46, wherein after said annealing, further comprising the followingsteps: selectively depositing a silicon-containing semiconductor suchthat it does not grow on said selective liner on vertical gate surface,implanting ions of a first conductivity type, annealing said implants,forming a gate electrode sidewall spacer, and selective deposition of asilicide layer on remaining silicon surfaces.
 68. The method of claim46, wherein after said annealing, further comprising the followingsteps: selectively depositing a silicon containing semiconductor suchthat it does not grow on said selective liner on vertical gate surface,implanting ions of a first conductivity type, implanting ions of asecond conductivity type, annealing to concurrently form a halo regionand drain and source extensions near the gate edge, forming a gateelectrode sidewall spacer, forming a blanket layer of metal over saidopenings, reacting said metal with said source and drain regions to forma stable silicide, and selectively wet etching to remove unreacted metalin regions where said spacer remains.
 69. The method of claim 46,wherein after said annealing, further comprising the following steps:selectively depositing a silicon containing semiconductor such that itdoes not grow on said selective liner on vertical gate surface,implanting ions of a first conductivity type, implanting ions of asecond conductivity type, annealing to concurrently form a halo regionand drain and source extensions near the gate edge, annealing of saidimplants, forming a gate electrode sidewall spacer, and selectivelydepositing a silicide layer on remaining silicon surfaces.
 70. Themethod of claim 44, wherein after selective anisotropic etching of saidliner, further comprising selectively depositing a silicon-containingsemiconductor such that it does not grow on said selective liner onvertical gate surface.
 71. The method of claim 45, wherein afterselective anisotropic etching of said liner, further comprisingselectively depositing a silicon-containing semiconductor such that itdoes not grow on said selective liner on vertical gate surface.
 72. Themethod of claim 70, wherein after selective silicon growth, furthercomprising the following steps: selectively removing said vertical linersuch that no liner remains on vertical surface of gate electrode,implanting ions of a first conductivity type, annealing to form drainand source extensions immediately next to the gate edge, forming a gateelectrode sidewall spacer, forming a blanket layer of metal over saidopenings, reacting said metal with said source and drain regions to forma stable silicide, and selectively wet etching to remove unreacted metalin regions where said spacer remains.
 73. The method of claim 71,wherein after selective silicon growth further comprising the followingsteps: selectively removing said vertical liner such that no linerremains on vertical surface of gate electrode, implanting ions of afirst conductivity type, annealing to form drain and source extensionsimmediately next to the gate edge, forming a gate electrode sidewallspacer, forming a blanket layer of metal over said openings, reactingsaid metal with said source and drain regions to form a stable silicide,and selectively wet etching to remove unreacted metal in regions wheresaid spacer remains.
 74. The method of claim 70, wherein after selectivesilicon growth, further comprising the following steps: selectivelyremoving said vertical liner such that no liner remains on verticalsurface of gate electrode, implanting ions of a first conductivity type,implanting ions of a second conductivity type, annealing to concurrentlyform a halo region and drain and source extensions immediately next tothe gate edge forming a gate electrode sidewall spacer, forming ablanket layer of metal over said openings, reacting said metal with saidsource and-drain regions to form a stable silicide, and selectively wetetching to remove unreacted metal in regions where said spacer remains.75. The method of claim 71, wherein after selective silicon growth,further comprising the following steps: selectively removing of saidvertical liner such that no liner remains on vertical surface of gateelectrode, implanting ions of a first conductivity type, implanting ionsof a second conductivity type, annealing to concurrently form a haloregion and drain and source extensions immediately next to the gateedge, forming a gate electrode sidewall spacer, forming a blanket layerof metal over said openings, reacting said metal with said source anddrain regions to form a stable silicide, and selectively wet etching toremove unreacted metal in regions where said spacer remains.
 76. Themethod of claim 54, wherein after anisotropic etching of said liner,further comprising the following steps: selectively depositing siliconcontaining semiconductor material such that growth occurs on the exposedsilicon and silicide regions, selectively removing said vertical linerof first material such that no liner remains on vertical surface of gateelectrode, implanting ions of a first conductivity type, and annealingto form a drain and source extensions immediately next to the gate edge.77. The method of claim 55, wherein after anisotropic etching of saidliner, further comprising the following steps: selectively depositingsilicon containing semiconductor material such that growth occurs on theexposed silicon and silicide regions, selectively removing said verticalliner of first material such that no liner remains on vertical surfaceof gate electrode, implanting ions of a first conductivity type, andannealing to form a drain and source extensions immediately next to thegate edge.
 78. The method of claim 56, wherein after anisotropic etchingof said liner, further comprising the following steps: selectivelydepositing silicon containing semiconductor material such that growthoccurs on the exposed silicon and silicide regions, selectively removingsaid vertical liner of first material such that no liner remains onvertical surface of gate electrode, implanting ions of a firstconductivity type, and annealing to form a drain and source extensionsimmediately next to the gate edge.
 79. The method of claim 57, whereinafter anisotropic etching of said liner, further comprising thefollowing steps: selectively depositing silicon containing semiconductormaterial such that growth occurs on the exposed silicon and silicideregions, selectively removing said vertical liner of first material suchthat no liner remains on vertical surface of gate electrode, implantingions of a first conductivity type, and annealing to form a drain andsource extensions immediately next to the gate edge.
 80. The method ofclaim 54, wherein after anisotropic etching of said liner, furthercomprising the following steps: selectively depositing siliconcontaining semiconductor material such that growth occurs on the exposedsilicon and silicide regions, selectively removing of said verticalliner of first material such that no liner remains on vertical surfaceof gate electrode, implanting ions of a first conductivity type,implanting ions of a second conductivity type, and annealing toconcurrently form a halo region and drain and source extensionsimmediately next to the gate edge.
 81. The method of claim 55, whereinafter anisotropic etching of said liner, further comprising thefollowing steps: selectively depositing silicon containing semiconductormaterial such that growth occurs on the exposed silicon and silicideregions, selectively removing said vertical liner of first material suchthat no liner remains on vertical surface of gate electrode, implantingions of a first conductivity type, implanting ions of a secondconductivity type, and annealing to concurrently form a halo and drainand source extensions immediately next to the gate edge.
 82. The methodof claim 56, wherein after anisotropic etching of said liner, furthercomprising the following steps: selectively depositing siliconcontaining semiconductor material such that growth occurs on the exposedsilicon and silicide regions, selectively removing of said verticalliner of first material such that no liner remains on vertical surfaceof gate electrode, implanting ions of a first conductivity type,implanting ions of a second conductivity type, and annealing toconcurrently form a halo region and drain and source extensionsimmediately next to the gate edge.
 83. The method of claim 57, whereinafter anisotropic etching of said liner, further comprising thefollowing steps: selectively depositing silicon containing semiconductormaterial such that growth occurs on the exposed silicon and silicideregions, selectively removing said vertical liner of first material suchthat no liner remains on vertical surface of gate electrode, implantingions of a first conductivity type, implanting ions of a secondconductivity type, and annealing to concurrently form a halo region anddrain and source extensions immediately next to the gate edge.
 84. Themethod of claim 54, wherein after anisotropic etching of said liner,further comprising the following steps: selectively depositing siliconcontaining semiconductor material, such that growth occurs on theexposed silicon and silicide regions, implanting ions of a firstconductivity type, and annealing to form a drain and source extensionsimmediately next to the gate edge.
 85. The method of claim 55, whereinafter anisotropic etching of said liner, further comprising thefollowing steps: selectively depositing silicon containing semiconductormaterial such that growth occurs on the exposed silicon and silicideregions, implanting ions of a first conductivity type, and annealing toform a drain and source extensions immediately next to the gate edge.86. The method of claim 56, wherein after anisotropic etching of saidliner, further comprising the following steps: selectively depositingsilicon containing semiconductor material such that growth occurs on theexposed silicon and silicide regions, and implanting ions of a firstconductivity type, and annealing to form a drain and source extensionsimmediately next to the gate edge.
 87. The method of claim 57, whereinafter anisotropic etching of said liner, further comprising thefollowing steps: selectively depositing silicon containing semiconductormaterial such that growth occurs on the exposed silicon and silicideregions, implanting ions of a first conductivity type, and annealing toform a drain and source extensions immediately next to the gate edge.88. The method of claim 54, wherein after anisotropic etching of saidliner, further comprising the following steps: selectively depositingsilicon containing semiconductor material such that growth occurs on theexposed silicon and silicide regions, implanting ions of a firstconductivity type, implanting ions of a second conductivity type, andannealing to concurrently form a halo region and drain and sourceextensions.
 89. The method of claim 55, wherein after anisotropicetching of said liner, further comprising the following steps:selectively depositing silicon containing semiconductor material suchthat growth occurs on the exposed silicon and silicide regions,implanting ions of a first conductivity type, implanting ions of asecond conductivity type, and annealing to concurrently form a haloregion and drain and source extensions.
 90. The method of claim 56,wherein after anisotropic etching of said liner, further comprising thefollowing steps: selectively depositing silicon containing semiconductormaterial such that growth occurs on the exposed silicon and silicideregions, implanting ions of a first conductivity type, implanting ionsof a second conductivity type, and annealing to concurrently form a haloand drain and source extensions.
 91. The method of claim 57, whereinafter anisotropic etching of said liner, further comprising thefollowing steps: selectively depositing silicon containing semiconductormaterial such that growth occurs on the exposed silicon and silicideregions, implanting ions of a first conductivity type, implanting ionsof a second conductivity type, and annealing to concurrently form a haloregion and drain and source extensions.
 92. The method of claim 4,wherein after selectively removing second material with respect to firstmaterial, further comprising the additional steps of: anisotropicallyetching said liner to form open source and drain regions of exposedsilicon, selectively depositing silicon containing semiconductormaterial such that growth occurs on the exposed silicon regions,implanting ions of a first conductivity type into said selective siliconlayer, annealing to form a drain and source extensions, forming a gateelectrode sidewall spacer, forming a blanket layer of metal over saidsilicon exposed regions, reacting said metal with said source and drainregions to form a stable silicide, and selectively wet etching to removeunreacted metal in regions where said spacer remains.
 93. The method ofclaim 4, wherein after selectively removing second material with respectto first material, further comprising the additional steps of:anisotropically etching said liner to form open source and drain regionsof exposed silicon, selectively depositing silicon containingsemiconductor material such that growth occurs on the exposed siliconregions, implanting ions of a first conductivity type into saidselective silicon layer, implanting ions of a second conductivity type,annealing to concurrently form a halo and drain and source extensions,forming a gate electrode sidewall spacer, forming a blanket layer ofmetal over said silicon exposed regions, reacting said metal with saidsource and drain regions to form a stable silicide, and selectively wetetching to remove unreacted metal in regions where said spacer remains.94. The method of claim 4, wherein after selectively removing secondmaterial with respect to first material, further comprising theadditional steps of: anisotropically etching said liner to form opensource and drain regions of exposed silicon, selectively depositingsilicon containing semiconductor material such that growth occurs on theexposed silicon regions, implanting ions of a first conductivity typeinto said selective silicon layer, annealing said layer, selectivelyremoving said vertical liner material, implanting ions of a firstconductivity type, annealing to form source and drain extension regionsimmediately adjacent to gate electrode, forming a gate electrodesidewall spacer, forming a blanket layer of metal over said siliconexposed regions, reacting said metal with said source and drain regionsto form a stable silicide, and selectively wet etching to removeunreacted metal in regions where said spacer remains.
 95. The method ofclaim 4, wherein after selectively removing second material with respectto first material, further comprising the additional steps of:anisotropically etching said liner to form open source and drain regionsof exposed silicon, selectively depositing silicon containingsemiconductor material such that growth occurs on the exposed siliconregions, implanting ions of a first conductive type into said selectivesilicon layer, annealing said layer, selectively removing said verticalliner material, implanting ions of a first conductivity type, implantingions of a second conductivity type, annealing to concurrently formsource and drain extension and halo regions immediately adjacent to gateelectrode, forming a gate electrode sidewall spacer, forming a blanketlayer of metal over said silicon exposed regions, reacting said metalwith said source and drain regions to form a stable silicide, andselectively wet etching to remove unreacted metal in regions where saidspacer remains.
 96. A method comprising: forming source and drainregions; forming source and drain contact regions; and thereafterforming source and drain extension regions.
 97. A method comprising:forming elevated and deep source and drain regions; forming source anddrain extension regions; and thereafter forming source and drain contactregions at a temperature up to about 600° C. and an annealing time up toabout one minute.